The present invention relates to the protection of semiconductor integrated circuits from static electricity. More particularly, this invention relates to a complementary silicon controlled rectifier (SCR) electrostatic discharge (ESD) protection circuit formed on a silicon substrate.
In order to reduce the layout area of very or ultra large scale integrated circuits, a CMOS chip of that size often has pin counts of more than two hundred pins. With such a large number of pins, the entire layout area of such a high-pin-count chip depends mostly on the pitch of input/output (I/O) pads and the electrostatic discharge protection circuits associated with the pins. If the layout areas of I/O pads with ESD protection circuits can be reduced that will improve the high speed performance of the chip due to the reduction of parasitic resistance and capacitance. However, the ESD efficiency may adversely affected as a result of smaller electrostatic current flow paths. The electrostatic protection capability of the ESD protection circuit should be enforced, or small geometry semiconductor devices in the VLSI chip can be damaged by static electricity.
Recently, a lateral SCR device has been used and proved beneficial in ESD protection circuits due to its high ESD failure threshold voltage and the fact that it lays out in a small area. See, for example, U.S. Pat. Nos. 5,140,401; 5,182,220; 4,896,234; 4,939,616; 5,010,380; 5,012,317 and 5,166,089. The ESD protection circuit, illustrated in FIG. 1, includes a first SCR 10 and a second SCR 20, coupled between voltage source V.sub.DD and ground V.sub.SS, and combined in a complementary mode.
First SCR 10 consists bipolar junction transistors (BJTs) Q1 and Q2. The base of Q1 and the collector of Q2 both coupled together and via a parasitic resistance R.sub.sub1 to an anode gate 4. Anode 3 of first SCR 10 is formed at one end of parasitic resistance R.sub.w1, which resistance is thence coupled to the emitter of Q1. The emitter of Q2 forms a cathode 2. The collector of Q1 and the base of Q2 both are coupled together and to cathode gate 1 through parasitic resistance R.sub.w2. Parasitic capacitors occur between electrodes of the BJTs: C.sub.e1 between the base and emitter of Q1, C.sub.c1 +C.sub.c2 between bases of Q1 and Q2, and C.sub.e2 between base and emitter of Q2.
Anode 3 and anode gate 4 of first SCR 10 are supplied with a supply voltage V.sub.DD. Cathode 1 coupled to an I/O pad 30 also is in electrical connection with internal circuitry 40 on the chip in which this circuit is formed. Cathode gate 1 of first SCR 10 is applied with voltage power supply V.sub.SS.
Second SCR 20 is also formed by two BJTs, namely Q3 and Q4. The base of Q3 and the collector of Q4 are both coupled together and via a parasitic resistance R.sub.sub2 to an anode gate 8 at a distal end of R.sub.sub2. An anode 7 of second SCR 20 is formed at one end of a parasitic resistance R.sub.w3, which resistance is coupled at its other end to the emitter of Q3. The emitter of Q4 forms a cathode 6 of SCR 20. The collector of Q3 and the base of Q4 are coupled together and to cathode gate 5 through resistance R.sub.w4. There are also parasitic capacitors formed between electrodes of the BJTs: C.sub.e3 between the base and emitter of Q3, C.sub.c3 +C.sub.c4 between bases of Q3 and Q4, and C.sub.e4 between the base and emitter of Q4.
Anode 7 of second SCR 20 is coupled to I/O pad 30 and also is in electrical connection with internal circuitry 40 of the VLSI chip. Cathode 6 and cathode gate 5 of second SCR 20 are supplied with supply voltage V.sub.SS. (i.e. ground). Anode gate 8 is coupled to supply voltage V.sub.DD.
An accompanying diode protection circuit 50 is also shown in the drawing. Circuit 50 is includes diodes D1 and D2. Diode D2 has its cathode 12 and anode 15 connected to parasitic resistance R.sub.sub2 and R.sub.w3 respectively, and electrically couple to voltage power supply V.sub.DD and I/O pad there through. Diode D1 couples I/O pad with its cathode 2, while its anode 14, through parasitic resistance R.sub.w2, is applied with voltage power supply V.sub.SS.
A cross-sectional view of the above-mentioned complementary-SCR ESD protection circuit as formed on a silicon substrate is shown in FIG. 2. The circuit is established in an N-type silicon substrate 12 utilizing standard CMOS processing. P-type wells are formed by diffusion of P-type dopant into the N-type substrate to form the complementary SCRs. First SCR 10 is formed by a parasitic lateral p-n-p BJT Q1 (please note elements 14-12-16) and a parasitic vertical n-p-n BJT Q2 (please note elements 2-14-12). Second SCR 20 is formed by a lateral p-n-p BJT Q3 (please note elements 13-12-15) and a vertical n-p-n BJT Q4 (please note elements 6-13-12). Lateral p-n-p BJTs Q1 and Q3 use p-type wells 15 and 16 instead of heavily doped p-type regions as emitters to increase their current gains. At the same time, the deeper the emitter of a lateral BJT, the larger amount of current can flow there through, and also the higher the failure threshold voltage.
Junction diodes D1 and D2, referring to FIG. 2, are in coincidence with base-emitter junctions of BJT Q2 and Q3, respectively. That is, the base-emitter junctions of the two BJTs also form diodes D1 and D2, and no additional diffusion region is necessary for the formation of the diodes. Diode D1 is formed by heavily doped n-type region 2 and P-type well 14, and D2 is formed by P-type well 15 and N-type substrate 12.
Since a CMOS VLSI circuit normally operates between a higher voltage V.sub.DD of 5V and a lower voltage V.sub.SS of 0V, diodes D1 and D2 provide a voltage-clamping circuit. Voltage levels of input signals are confined to a range of -0.5 to +5.5V by the voltage clamping effect of diodes D1 and D2. Although diodes D1 and D2 coincide with emitters of BJTs Q2 and Q3, the current flow paths through diodes are not the same as that through SCRs 10 and 20. Therefore, as diodes D1 or D2 conduct due to an over voltage condition at I/O pad 30, lateral SCRs 10 and 20 with their high impedance states are not triggered on.
There are four categories of ESD-stress at the input pad with positive or negative polarities respect to voltage power supply V.sub.DD or V.sub.SS. They are:
1. Diode D1 conducts forwardly to bypass ESD current but second SCR 20 is in its off state, if ESD-stress is negative polarity respect to V.sub.SS ;
2. Diode D2 conducts forwardly to bypass ESD current but first SCR 10 is in its off state, if ESD-stress is positive polarity respect to V.sub.DD ;
3. Second SCR 20 is triggered on to bypass ESD current but diode D1 is off, if ESD-stress is positive polarity respect to V.sub.SS ; and
4. First SCR 10 is triggered on to bypass ESD current but diode D2 is off, if ESD-stress is negative polarity respect to V.sub.DD.
However, there exists a parasitic latch-up path between voltage power supplies V.sub.DD and V.sub.SS in the above described ESD protection circuit. The so-called V.sub.DD -to-V.sub.SS latch-up path is contributed by BJT Q4 and parasitic BJT Q5, referring to FIG. 3, wherein Q4 is the same n-p-n BJT previously described with reference to second SCR 20. The V.sub.DD -to-V.sub.SS latchup path is shown by the dashed line in FIG. 3. As can be seen in FIG. 2, BJT Q5 has its emitter formed by P-type well 16, that is, the emitter of Q1, its base by a relatively wide spacing in N-type substrate 12, and its collector by P-type well 13, that is, also the collector of Q4. If first and second SCRs 10 and 20 are separated by a relatively wide pad layout, BJT Q5 will have a very small beta gain due to the relatively large size of its base width. Beta gain of vertically oriented BJT Q4 can also be reduced by enlarging the depth difference of its emitter doping region 6 and P-type well 13. However, the beta gain of a vertical BJT constructed using submicron CMOS technology is ordinarily as high as 100 to 200, and thus V.sub.DD -to-V.sub.SS latch-up may occur in the ESD protection circuit if resistance R.sub.sub1 and R.sub.w4 are large enough. If R.sub.sub1 and R.sub.w4 are reduced, the V.sub.DD -to-V.sub.SS latchup can be overcome.